The present disclosure relates to semiconductor devices and methods of manufacturing the devices, and more particularly to an effective technology for manufacturing semiconductors aimed at preventing an increase in resistance of an interconnection caused by disconnection at a PN boundary of a metal silicide layer in a Dual Metal Gate (DMG) process with a Metal inserted Poly-Si Stack (MIPS) structure, without sacrificing high integration of the devices due to an increase in the width of an interconnection of a gate electrode or the like.
In recent years, with high integration and minimization of semiconductor devices, minimized transistors have been rapidly developed. Accordingly, thicknesses of gate insulating films of transistors have decreased. However, a decrease in the thickness of a conventional gate insulating film of SiO2 or SiON causes a non-negligible increase in the value of a gate leakage current. As such, the use of a high dielectric constant film (hereinafter referred to as a High-k film) as a gate insulating film has been considered. When a High-k film having a high dielectric constant is used as a gate insulating film, a large actual physical film thickness can be secured to prevent a tunnel current, and an equivalent oxide thickness (EOT) can be reduced to enhance driving force of the transistor and to lower the power consumption.
With respect to a gate electrode, with minimization of a transistor, depletion of an electrode causes a decrease in capacitance. The decrease in the capacitance is equivalent to a 0.4 nm increase in the film thickness in terms of the thickness of a silicon dioxide film, when polysilicon is used as the material of a gate electrode as conventionally done. This value is large and not negligible compared to the thickness of a gate insulating film, which is expected to be reduced. The use of metal for a gate electrode has been considered, instead of polysilicon used conventionally. With the use of a metal gate electrode, the above-described gate depletion can be prevented. However, in order to apply a metal gate electrode to a High-k gate insulating film, an appropriate metal material needs to be selected for each of an N-type metal-insulator-semiconductor (MIS) transistor (hereinafter referred to as “NMIS transistor” or “NMIS”) and a P-type MIS transistor (hereinafter referred to as “PMIS transistor” or “PMIS”).
Metal gate processes can be divided into two major types: a gate-first process, and a gate-last process. In the gate-first process, after forming a gate electrode, the step of forming a transistor is performed, which includes ion implantation and heat treatment. On the other hand, in the gate-last process, after forming a transistor using a dummy gate, the dummy gate is removed to form a gate electrode. Thus, the gate-last process is more difficult than the gate-first process. Therefore, formation of a metal gate electrode using the gate-first process is now considered. In the gate-first process, a MIPS structure is generally used in view of its processability into a gate and its consistency with a complementary metal oxide semiconductor (CMOS) process.
As described above, employing a High-k gate insulating film and a DMG having a MIPS structure has been considered as a next generation process (see, for example, S. C. Song et al. “Highly Manufacturable 45 nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration,” VLSI Technology, Aug. 6, 2006, p. 16: hereinafter referred to as “Non-Patent Document 1”).
FIG. 17 is a cross-sectional view illustrating a semiconductor device including a DMG having a MIPS structure shown in Non-Patent Document 1, and is specifically a cross-sectional view of a transistor taken in a gate width direction (W direction). As shown in FIG. 17, an isolation formation region RC in a semiconductor substrate 1 is provided with an isolation region 2 including a shallow trench isolation (STI) for segmenting a first active region 1A, which is the semiconductor substrate 1 of an NMIS formation region RA, and a second active region 1B, which is the semiconductor substrate 1 of a PMIS formation region RB. A P-well region 1a is formed in the first active region 1A of the NMIS formation region RA surrounded by the isolation region 2, and an N-well region 1b is formed in the second active region 1B of the PMIS formation region RB surrounded by the isolation region 2. A metal gate electrode 4a is formed on the first active region 1A with a gate insulating film 3a interposed therebetween. A metal gate electrode 4b is formed on the second active region 1B with a gate insulating film 3b interposed therebetween. A polysilicon film 6 is continuously formed on the metal gate electrodes 4a and 4b, and on the isolation region 2 located between the two electrodes. The polysilicon film 6 is processed into a form of a gate electrode, which includes an interconnection for electrically connecting the metal gate electrodes 4a and 4b. The surface of the polysilicon film 6 is silicided, thereby forming a silicide layer 7. Although not illustrated, an impurity region such as a source/drain region is formed in each of the MIS formation regions RA and RB by an ion implantation step or a heat treatment step to form a transistor structure.